Due to the requirement of high integration, the scales of semiconductor devices must be reduced. Accordingly, the capacitance of a capacitor structure existing in a memory device such as a dynamic random access memory (DRAM) cell may be influenced by the reduced area of the device on the wafer. A small capacitance of a memory cell will make the data reading/writing process of the memory cell be easily influenced by noises and thus cannot proceed normally. To increase the capacitance on a limited area without influencing the integration, a capacitor structure as illustrated in FIG. 1 is applied by most conventional DRAM cells. The conventional DRAM cell includes a metal-oxide-semiconductor (MOS) transistor 11, a bit line structure 12, and the capacitor structure constructed by the electrode layers 13, 15 and the dielectric layer 14. For maintaining a sufficient capacitance, the height of the capacitor structure is extended to increase the effective capacitor junction area (i.e. the real area of the dielectric layer) without affecting the integration of the devices on the wafer. However, such an extension will cause a serious problem: an up-and-down topography 16. Such a topography may cause an up-and-down surface of the other substance such as a metal layer formed in the succeeding procedures. If a photolithography procedure is applied on the metal layer, due to the limitation of depth of focus of the photolithography procedure, the high reflectivity and the up-and-down surface of the metal layer, the pattern on the photoresistant cannot be defined exactly. In a high integration wafer, such a distortion may narrow or even disconnect the metal lines, and therefore reduce the yield. It is than attempted by the Applicant to deal with the abovementioned problem.